114 年 國立中山大學資訊工程學系碩士班甲組《計算機結構》
第 1 題18 分
- (18%) A memory system is composed of eight banks, and each bank contains rows. Every DRAM
row refresh is initiated by a command from the memory controller, and it refreshes a single row in a single
DRAM bank. Each refresh command keeps the command bus busy for 5ns. We define command bus
utilization as the fraction of total execution time during which the command bus is occupied.
1.1 (6%) Given that the refresh interval is 64ms, calculate the command bus utilization of refresh
commands. Show your work step-by-step.
1.2 (12%) If 70% of all rows can withstand a refresh interval of 256ms, how does the command bus
utilization of refresh command change? Calculate the reduction in bus utilization. Show your
work step-by-step.
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1.1
關鍵步驟:
-
計算記憶體系統總 Row 數:
-
計算在單一刷新週期()內 Command Bus 佔用的總時間:
-
計算 Command Bus 利用率:
【答案】 Command Bus 利用率為 (或 )。
1.2
關鍵步驟:
- 計算單一 Row 的平均刷新次數比例:
以 為共同週期計算:
第 2 題14 分
- (14%) Assume we have a virtual memory detailed as follows:
• 256 MiB Physical Address Space
• 4 GiB Virtual Address Space
• 1 KiB page size
• A TLB with 4 sets that is 8-way associative with LRU replacement
2.1 (10%) How many bits will be used for page offset, Virtual Page Number (VPN), Physical Page Number (PPN), TLB index, and TLB tag?
2.2 (4%) How many entries are in this page table?
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核心觀念
虛擬記憶體位址可分為:
實體記憶體位址可分為:
其中:
- Page Offset:頁面內的位移,取決於頁面大小。
- VPN(Virtual Page Number):虛擬頁編號。
- PPN(Physical Page Number):實體頁框編號。
- TLB index:決定查詢哪一個 TLB set。
- TLB tag:在該 set 中比對的標籤,通常由 VPN 扣除 index bits 得到。
TLB 為 4 sets、8-way associative,因此總共有:
個 TLB entries。LRU 只影響替換順序,不影響位元數計算。
解題方法
先將所有容量寫成 的次方,再依序計算頁面位移、VPN、PPN,以及 TLB 的 index 與 tag。
1. Page Offset bits
頁面大小為 :
因此頁面內位移需要:
2. Virtual Page Number(VPN)bits
虛擬位址空間為 :
虛擬位址總長度為 bits。扣除 bits 的 page offset:
因此:
虛擬頁面的總數也就是:
3. Physical Page Number(PPN)bits
實體位址空間為 :
實體位址長度為 bits。扣除 bits 的 page offset:
因此:
4. TLB index bits
TLB 有 4 個 sets,因此 index 需要能表示 4 種 set:
因此:
5. TLB tag bits
TLB 通常以 VPN 查詢。VPN 中有 bits 用作 set index,其餘位元作為 tag:
因此:
第 3 題18 分
- (18%) Assume a machine with a 7-stage pipeline. Assume that branches are resolved in the sixth stage.
Assume that 20% of instructions are branches.
3.1 (4%) How many instructions of wasted work are there per branch misprediction on this machine?
3.2 (4%) Assume N instructions are on the correct path of a program and assume a branch predictor
accuracy of A. Write the equation for the number of instructions that are fetched on this machine in terms
of N and A. (Show your work step by step)
3.3 (4%) Let's say we modify the machine so that it uses dual path execution (where an equal number of
instructions are fetched from each of the two branch paths). Assume branches are resolved in the sixth stage. Write how many instructions would be fetched in this case, as a function of N. (Show your work step by step)
3.4 (6%) Now let's say that the machine combines branch prediction and dual path execution in the
following way: A branch confidence estimator is used to gauge how confident the machine is of the prediction
made for a branch. When confidence in a prediction is high, the branch predictor's prediction is
used to fetch the next instruction; when confidence in a prediction is low, dual path execution is used
instead. Assume that the confidence estimator estimates a fraction C of the branch predictions have high
confidence, and that the probability that the confidence estimator is wrong in its high confidence estimation
is M. Write how many instructions would be fetched in this case, as a function of N, A, C, and M. (Show
your work step by step)
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3.1
解題觀念
當分支指令在第 6 階段確定結果時,代表管線在確定結果前已擷取了後續指令。一旦發生分支猜錯(Misprediction),這些已擷取的指令皆屬錯誤路徑,必須全部清空(Flush)。
推導步驟
- 分支指令於第 1 階段擷取,至第 6 階段解析完成。
- 在第 2 至第 6 階段期間,管線已接續擷取了 個後續指令。
- 當分支預測錯誤時,這 5 個指令皆為無用工作(Wasted work)。
【答案】5 個指令
3.2
解題觀念
總擷取指令數等於正確路徑指令數加上因分支猜錯而額外擷取的錯誤路徑指令數。
推導步驟
- 正確路徑指令數為 。
- 題目給定分支指令佔總指令數的 20%,故分支指令總數為 。
- 分支預測正確率為 ,則猜錯率為 ,猜錯的分支數量為 。
- 每次猜錯會浪費 5 個指令,故因猜錯而擷取的額外指令數為:
- 總擷取指令數 為:
【答案】
3.3
解題觀念
雙路徑執行(Dual Path Execution)會在遇到分支時,同時從「跳躍(Taken)」與「不跳躍(Not-Taken)」兩條路徑擷取等量的指令。
第 4 題14 分
- (14%) Suppose that (after optimization) a typical n-instruction program requires an additional 4*n NOP
instructions to correctly handle data hazards.
4.1 (4%) Suppose that the cycle time of this pipeline without forwarding is 250 ps. Suppose also that adding
forwarding hardware will reduce the number of NOPs from to , but increase the cycle time
to 300 ps. What is the speedup of this new pipeline compared to the one without forwarding?
4.2 (4%) Can a program with only NOPs possibly run faster on the pipeline with forwarding?
Explain why or why not.
4.3. (6%) At minimum, how many NOPs (as a percentage of code instructions) must a program have before
it can possibly run faster on the pipeline with forwarding?
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核心觀念
本題考查計算機結構中的 管線效能分析(Pipeline Performance Analysis)、資料冒險(Data Hazards) 以及 前推機制(Forwarding / Bypassing) 對時脈週期時間(Clock Cycle Time, CCT)與執行時間(Execution Time)的權衡(Trade-off)。
-
程式執行時間公式:
在 steady state 假設下,每執行一條指令(包含 NOP)耗費 個週期(CPI = 1),因此總週期數等於總指令數:
-
加速比(Speedup):
-
硬體設計權衡(Trade-off):
引入 Forwarding 硬體可以減少控制/資料相依所產生的 NOP(停頓週期),但額外增加的旁路邏輯與多工器(Mux)會拉長關鍵路徑(Critical Path),進而增加時脈週期時間(從 增加至 )。只有當減少 NOP 所節省的週期比例大於週期時間拉長的比例時,整體效能才會提升。
(註:題幹前言寫著 係考題印刷誤植,子題 4.1 已明確給出無前推時的 NOP 數量為 。解題統一採子題 4.1 設定之 進行精確推導。)
解題方法
採用「量化執行時間比較法」:
- 子題 4.1:分別計算無前推(Without Forwarding)與有前推(With Forwarding)兩種架構下的總執行時間 與 ,再相除求出 Speedup。
- 子題 4.2:計算當無前推管線僅需 個 NOP 時的執行時間,並與前推架構的「理論極限最佳時間」(即 NOP 降為 時)進行比較。
- 子題 4.3:設無前推管線下的 NOP 比例為 ,列出前推架構「最佳狀況執行時間 」的不等式,解出臨限值(Threshold)。
子題詳解與分析
4.1 (4%) 加速比計算
-
無前推管線(Without Forwarding):
- NOP 數量 =
- 總指令/週期數 =
- 時脈週期時間
- 總執行時間:
-
具前推管線(With Forwarding):
- NOP 數量 =
- 總指令/週期數 =
- 時脈週期時間
- 總執行時間: