112 年 國立中山大學電機工程學系碩士班己組《計算機結構》

Assume that A, B, C, and D are well-represented as the 32-bit single-precision format in IEEE-754 standard as shown in TABLE I. Please answer the following questions.

TABLE I

(a) (10%) If $X = A \times B$, please calculate the value of $X$ and represent it as the binary format in IEEE-754 standard, including 1-bit Sign (S), 23-bit Mantissa (M), and 8-bit Exponent (E).
(i) (2%) Please show S in binary.
(ii) (4%) Please show E in binary.
(iii) (4%) Please show M in binary.

(b) (10%) If $Y = \frac{C}{D}$, please calculate the value of $Y$ and represent it as the binary format in IEEE-754 standard, including 1-bit Sign (S), 23-bit Mantissa (M), and 8-bit Exponent (E).
(i) (2%) Please show S in binary.
(ii) (4%) Please show E in binary.
(iii) (4%) Please show M in binary.

Assume that the address size of the cache is 32 bits. If the total number of bits in a "direct-mapped" cache is 274K-bit, where K denotes 1024, please answer the following questions.
(a) (10%) How many total data does the cache store (represented in "KB")?
(b) (10%) Please calculate the corresponding block size (represented in "word").
(c) (5%) If we want to keep the same number of index bits in the address and change it as "4-way set associative", what is the total number of tag bits in this new-type cache (represented in "Kbit")?

Assume that a sorting program is divided into 3 portions, {X, Y, Z}, which they have individual CPIs without memory stalls, i.e., $CPI_x = 5$, $CPI_y = 3$, and $CPI_z = 4$. We only know X and Y have instruction count of 38 and 46, respectively. Unfortunately, the instruction count of Z is unknown. One day, this sorting program is modified with memory stall. The individual instruction count keeps the same. The clock cycle time is also without change. But the CPIs are modified due to any type of cache miss. Assume the instruction cache miss rate for this sorting program is 3% and the data cache miss rate is 4%. Suppose 23% of the instructions executed are loads (Iw) and stores (sw). The miss penalty is 100 cycles for all misses. Under this situation, the new CPU time is two times of the original CPU time. Please answer the following questions.
(a) (5%) Please calculate the original CPI for the sorting program without memory stalls.
(b) (5%) Please calculate the instruction count of Z.

The following MIPS assembly codes show a simple program regarding the three data arrays, X[i], Y[i], and Z[i]. All the numbers specified in the instruction set are represented as the decimal format. We know that the base address of X[i], Y[i], and Z[i] is stored in $a0,$a1, and $a2, respectively. In addition, only the first element in each of data arrays is non-zero, such as X[0] = 36, Y[0] = 21, and Z[0] = 41; other elements are all-zeros. Please answer the following questions.
(a) (5%) Please calculate Y[3].
(b) (5%) After executing this program, please find out N when X[N] > 0 and X[N+1] = 0.
(c) (5%) According to the result in (b), please calculate X[N].
(d) (5%) According to the result in (b), please calculate Y[N].
(e) (5%) According to the result in (b), please calculate Z[N].

Assembly Code:
0x100 sub $t0,$0, $0 0x110 add$s1, $a0,$t0
0x120 lw $t2, 0 ($s1)
lw $t3, 0 ($s2)
lw $t4, 0 ($s3)
0x130 sub $t6,$t6, $t4 srl$t7, $t3, 1 0x140 add$s3, $a2,$t1
sw $t7, 4 ($s1)
sw $t6, 4 ($s2)
sw $t5, 4 ($s3)
addi $t0,$t0, 1
bne $s0,$t0, -72
0x150 EXIT

(Note: Some instructions are missing from the provided code snippet. I will fill in the most probable ones based on context and typical MIPS patterns.)

Figure 1 depicts a multi-cycle MIPS CPU implementation. A program takes 60 clock cycles in total, as listed in TABLE II. All the instructions utilized only belong to the categories of {R-type, SW, LW, BEQ, Jump}. All the control signals are specified in the decimal format and "X" denotes "don't care". According to Figure 1 and TABLE II, please answer the following questions.
(a) (4%) What is the total number of instructions used for this program?
(b) (4%) Please show the single-bit value of "lorD" at 33rd clock cycle.
(c) (4%) Please show the 2-bit binary value of "PCsource" at 47th clock cycle.
(d) (4%) "opcode" is the most important for deciding what instruction is decoded currently. It has 6 bits in the 32-bit instruction format, such as Bit [31:26]. What is the decimal value of "opcode" for the instruction executed at 13th clock cycle?
(e) (4%) What is the number of SW instruction?

[FIGURE 1: Multi-cycle MIPS CPU Implementation Diagram]
[TABLE II: Control Signals for Each Clock Cycle]